Test and Debug in Deep-Submicron Technologies

With the scaling of feature sizes into Deep-Submicron (DSM) values, the level of integration and performance achievable in VLSI chips increases. A lot of work has been directed to tackle design related issues arising out of scaling, like leakage mitigation etc. However efforts to enhance testability of such designs have not been sufficient. It is not viable to overlook testability issues arising out of these designs because the defect sizes do not scale proportional to the feature sizes. Previously effective fault models like stuck-at appear archaic and are unable to model faults accurately. This necessitates the need for more detailed models which can more explicitly model the behavior of faulty DSM chips. Also there is a significant increase in delay faults in logical paths of integrated circuits. Delay faults cause the delay of paths in a chip to be larger than expected resulting in the output of a chip to be deviant from the expected behavior, in spite of the chip being functionally correct. Efficient techniques are needed for detecting such defects in first silicon and eliminating them before the final versions of the chips are shipped. This requires efficient debug techniques for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. In this paper we present an insight into test challenges arising out of deep submicron technologies and effective approaches to tackle the same.